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| LCDP1521 Dual line programmable transient voltage suppressor for SLIC protection Features Dual line programmable transient voltage suppressor Wide negative firing voltage range: VMGL = -150 V max. Low dynamic switching voltages: VFP and VDGL Low gate triggering current: IGT = 5 mA max Peak pulse current: IPP = 20 A (10/1000 s) Holding current: IH = 150 mA min SO-8 Description This device has been especially designed to protect 2 new high voltage, as well as classical SLICs, against transient overvoltages. Positive overvoltages are clamped by 2 diodes. Negative surges are suppressed by 2 thyristors, their breakdown voltage being referenced to -VBAT through the gate. This component presents a very low gate triggering current (IGT) in order to reduce the current consumption on printed circuit board during the firing phase. Functional diagram TIP 1 1 8 RING 1 GATE 2 7 GND GATE 3 6 GND Benefits Trisils are not subject to ageing and provide a fail safe mode in short circuit for a better protection. Trisils are used to help equipment to meet various standards such as UL1950, IEC950 / CSA C22.2, UL1459 and FCC part68. Trisils have UL94 V0 resin approved (Trisils are UL497B approved (file: E136224)). TIP 2 4 5 RING 2 February 2006 www.st.com Rev 3 1/11 11 1 Compliant with the following standards LCDP1521 1 Compliant with the following standards Minimum serial resistor to meet standard () 31 40 62 7 200 20 0 0 120 40 27 0 120 27 43 32 0 STANDARD Peak Surge Voltage (V) 2500 1000 5000 1500 6000 1500 8000 15000 4000 2000 4000 2000 4000 4000 1500 800 1000 Voltage Waveform 2/10 s 10/1000 s 2/10 s 2/10 s 10/700 s 1/60 ns 10/700 s 1.2/50 s 10/700 s 1.2/50 s 10/160 s 10/560 s 9/720 s Required peak current (A) 500 100 500 100 150 37.5 Current Waveform 2/10 s 10/1000 s 2/10 s 2/10 s 5/310 s GR-1089 Core First level GR-1089 Core Second level GR-1089 Core Intra-building ITU-T-K20/K21 ITU-T-K20 (IEC61000-4-2) VDE0433 VDE0878 IEC61000-4-5 FCC Part 68, lightning surge type A FCC Part 68, lightning surge type B ESD contact discharge ESD air discharge 100 50 100 50 100 100 200 100 25 5/310 s 1/20 s 5/310 s 8/20 s 10/160 s 10/560 s 5/320 s 2 2.1 Characteristics Thermal resistance Symbol Rth (j-a) Parameter Junction to ambient Value 170 Unit C/W 2/11 LCDP1521 2 Characteristics 2.2 Electrical characteristics (TAMB = 25C) Symbol IGT IH IRM IRG VRM VGT VF VFP VDGL VGATE VRG C Parameter Gate triggering current Holding current Reverse leakage current LINE / GND Reverse leakage current GATE / LINE Reverse voltage LINE / GND Gate triggering voltage Forward drop voltage LINE / GND Peak forward voltage LINE / GND Dynamic switching voltage GATE / LINE IPP VR VRM VF IRM IR IH I V GATE / GND voltage Reverse voltage GATE / LINE Capacitance LINE / GND 2.3 Absolute ratings (Tamb = 25 C, unless otherwise specified). Symbol Parameter 10/1000 s 8/20 s 10/560 s 5/310 s 10/160 s 1/20 s 2/10 s t = 10ms t = 1s t = 10 ms t = 10 ms -40 C < Tamb < +85 C -40 C < Tamb < +85 C Value 20 60 20 25 30 60 70 5 3.5 0.125 2 -150 -150 - 55 to + 150 150 260 Unit IPP Peak pulse current (see note1) A ITSM I2t IGSM VMLG VMGL Tstg Tj TL Non repetitive surge peak on-state current (50 Hz sinusoidal) I2t value for fusing (50 Hz sinusoidal) Maximum gate current (50 Hz sinusoidal) Maximum voltage LINE/GND Maximum voltage GATE/LINE Storage temperature range Maximum junction temperature Maximum lead temperature for soldering during 10 s A A2s A V C C 3/11 2 Characteristics LCDP1521 Repetitive peak pulse current % IPP Figure 1. tr: rise time (s) tp: pulse duration (s) ex: Pulse waveform 10/1000 s tr = 10s tp = 1000 s 100 50 0 tr tp t 2.4 Parameters related to the diode line / GND (Tamb = 25C) Symbol VF VFP (Note 1) 10/700 s 1.2/50 s 2/10 s IF = 1 A 1.5 kV 1.5 kV 2.5 kV Test conditions t = 500 s RS = 110 RS = 60 RS = 245 IPP = 10 A IPP = 15 A IPP = 10 A Max 2 5 10 20 Unit V V Note: 1 See test circuit for VFP; RS is the protection resistor located on the line card. 2.5 Parameters related to the protection thyristor (Tamb = 25C unless otherwise specified) Symbol IGT IH VGT IRG VGND / LINE = -48 V VGATE = -48 V (Note 2) at IGT VRG = -150 V VRG = -150 V VGATE = -48 V VDGL 10/700 s 1.2/50 s 2/10 s (Note 3) 1.5 kV 1.5 kV 2.5 kV RS = 110 RS = 60 RS = 245 IPP = 10 A IPP = 15 A IPP = 10 A 5 10 20 Tc=25C Tc=85C Test conditions Min 0.1 150 2.5 5 50 Max 5 Unit mA mA V A V 2 See functional holding current (IH) test circuit 3 See test circuit for VDGL. The oscillations with a time duration lower than 50ns are not taken into account 4/11 LCDP1521 3 Functional holding current (IH) test circuit: go no-go test 2.6 Parameters related to diode and protection thyristor (Tamb = 25 C, unless otherwise specified) Symbol IRM C Test conditions VGATE / LINE = -1V VGATE / LINE = -1V VRM = -150 V VRM = -150 V Tc=25 C Tc=85 C 20 48 Typ. Max. 5 50 Unit A VR = 50 V bias, VRMS = 1 V, F = 1 MHz VR = 2 V bias, VRMS = 1 V, F = 1 MHz pF 3 Functional holding current (IH) test circuit: go no-go test R Surge generator VBAT = - 100V D.U.T This is a GO-NO GO test which confirms the holding current (IH) level in a functional test circuit. TEST PROCEDURE : - Adjust the current level at the IH value by short circuiting the D.U.T. - Fire the D.U.T. with a surge current : IPP = 10 A, 10/1000 s. - The D.U.T. will come back to the off-state within a duration of 50 ms max. 5/11 4 Test circuit for vfp and vdgl parameters LCDP1521 4 Test circuit for vfp and vdgl parameters (VP is defined in unload condition) R4 TIP R2 RING R3 L VP C1 R1 C2 GND Table 1. Test circuit component values Vp (V) 1500 1500 2500 C1 (F) 20 1 10 C2 (nF) 200 33 0 L (H) 0 0 1.1 R1 () 50 76 1.3 R2 () 15 13 0 R3 () 25 25 3 R4 () 25 25 3 IPP (A) 10 15 10 Rs () 110 60 245 Pulse (s) tr 10 1.2 2 tp 700 50 10 5 Technical information Figure 2. LCDP1521 concept behavior. Rs1 L1 TIP IG ID1 T1 Gate Th1 D1 GND V Tip GND -Vbat C Rs2 RING VRing L2 Figure 2 shows the classical protection circuit using the LCDP1521 crowbar concept. This topology has been developed to protect the new high voltage SLICs. This supports the programming of the negative firing threshold while the positive clamping value is fixed at GND. 6/11 LCDP1521 5 Technical information When a negative surge occurs on one wire (L1 for example), a current IG flows through the base of the transistor T1 and then injects a current in the gate of the thyristor Th1. Th1 fires and all the surge current flows through the ground. After the surge when the current flowing through Th1 becomes less negative than the holding current IH, then Th1 switches off. When a positive surge occurs on one wire (L1 for example), the diode D1 conducts and the surge current flows through the ground. The capacitor C is used to speed up the crowbar structure firing during the fast surge edges. This mimimizes the dynamic breakover voltage at the SLIC Tip and Ring inputs during fast strikes. Note that this capacitor is generally present around the SLIC - VBAT pin. So, to be efficient, it has to be as close as possible to the LCDP1521 Gate pin and to the reference ground track (or plan). The optimized value for C is 220 nF. The series resitors Rs1 and Rs2 in Figure 2 represent the fuse resistors or the PTC which are mandatory to withstand the power contact or the power induction tests imposed by the various country standards. Taking into account this fact, the actual lightning surge current flowing through the LCDP is equal to: I surge = V surge / (Rg + Rs) With V surge = peak surge voltage imposed by the standard. Rg = series resistor of the surge generator Rs = series resistor of the line card (equivalent to PTC + R on Figure 3.) Example: For a line card with 60 of series resistors which has to be qualified under GR1089 Core 1000V 10/1000s surge, the actual current through the LCDP1521 is equal to: I surge = 1000 / (10 + 60) = 14A The LCDP1521 is particularly optimized for the new telecom applications such as the fiber in the loop, the WLL, the remote central office. In this case, the operating voltages are smaller than in the classical system. This makes the high voltage SLICs particularly suitable. The schematics of Figure 3 shows the topologies most frequently used for these applications. Figure 3. Protection of high voltage SLICs -Vbat PTC or Fuse R LCDPxxxx TIP Line 1 Ring relay 1 SLIC 1 R PTC or Fuse RING PTC or Fuse R Ring relay 2 Line 2 SLIC 2 R PTC or Fuse 7/11 6 Ordering information scheme LCDP1521 Figure 4. Surge peak current versus overload duration. ITSM(A) 7 6 5 4 3 2 1 t(s) 0 0.01 0.10 1.00 10.00 100.00 1000.00 F=50Hz Tj initial=25C Figure 5. Relative variation of holding current versus junction temperature IH ( Tj ) / IH ( Tj=25C ) 1.3 1.2 1.1 1 0.9 0.8 Tj ( C ) 0.7 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 6 Ordering information scheme LCDP Line Card Dual Protection Holding Current 15 = 150 mA Version 2 = devices protected 15 2 1 RL Package 1 = SO-8 Packaging Blanck = Tube RL = Tape & Reel 8/11 LCDP1521 7 Package mechanical data SO-8 (Plastic) 7 Package mechanical data SO-8 (Plastic) DIMENSIONS REF. Millimetres Min. L c1 C a a2 A Inches Min. Typ. Max. 0.069 0.010 0.065 0.033 0.019 0.010 0.020 Typ. Max. 1.75 A a1 a2 a3 0.65 0.35 0.19 0.25 0.50 0.1 0.25 0.004 1.65 0.85 0.025 0.48 0.014 0.25 0.007 0.50 0.010 45 (typ) b e3 e S E a1 b b b1 D M C c1 8 5 F D E e e3 F L M S 4.8 5.8 1.27 3.81 3.8 0.4 5.0 6.2 0.189 0.228 0.050 0.150 0.197 0.244 1 4 4.0 0.15 0.157 0.050 0.024 1.27 0.016 0.6 8 (max) 8 Ordering Information Order code LCDP1521 LCDP1521RL(1) 1. Preferred device Marking CDP152 CDP152 Package SO-8 SO-8 Weight 0.08 g 0.08 g Base qty 100 2500 Delivery mode Tube Tape and Reel 9/11 9 Revision history LCDP1521 9 Revision history Date March 2002 24-Jun-2005 07-Feb-2006 Revision 1 2 3 Initial release. Peak Pulse Current changed from 15 to 20 A (10/1000 s) Added footnote to ordering information table Changes 10/11 LCDP1521 9 Revision history Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 11/11 |
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